Bøker av Svetlana N. Yanushkevich

Noise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed -- as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation -- specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementation of the MRF model by a new type of binary decision diagram (BDD), called a cyclic BDD. In this approach, logic gates and circuits are designed using 2-to-1 bi-directional switches. Such circuits are often modeled using Shannon expansions with the corresponding graph-based implementation, BDDs. Simulation experiments are reported to show the noise immunity of the proposed structures. Audiences who may benefit from this lecture include graduate students taking classes on advanced computing device design, and academic and industrial researchers. Table of Contents: Introduction to probabilistic computation models / Nanoscale circuits and fluctuation problems / Estimators and Metrics / MRF Models of Logic Gates / Neuromorphic models / Noise-tolerance via error correcting / Conclusion and future work

Decision diagram (DD) techniques are popular in the electronic design automation (EDA) of integrated circuits, and for good reason. Presenting DD techniques from an applied perspective, this book provides a comprehensive collection of DD techniques. It collects the theory, methods, and practical knowledge necessary to design advanced circuits.

A guide to design and analysis of nanoICs using CAD. It offers an introduction to the directions and basic methodology of logic design at the nanoscale, then proceeds to nanotechnologies and CAD, word-level and linear word-level data structures, 3-D topologies based on hypercubes and fault-tolerant computation in hypercube-like structures.