Enhancing DRAM Performance using Leakage Reduction Technique

Retention time is an important phenomenon in dynamic random access memory for data storage operation. The storage capacitor is solely responsible for charge storing mechanism. The overall action is control by word line and bit line. It is also responsible for sensing, monitoring and data storing operation. Normally the availability of inexpensive leakage reduction technique is the backbone of any dynamic random access memory wherein the valuable sense information is deposited in storage capacitance in electric charge form. Since there is no option available for replenishing the electric charge on storage capacitor to prevent loss of information or data.

One of the most acclaimed and accepted schemes toward effecting high retention time is by incorporating the leakage reduction technique which has becomes a part of dynamic random access memory.

Semiconductor memory finds its application in almost all the electronics fields comprises data sensing, monitoring and data storing operation. In computer, tablet, cell phones, real time data acquisition system, healthcare, military and many more. In most of these applications there are requirements of data sense, preserve and processing in real time operation. In other words, this selection of memories based on the types of data stored in semiconductor memory i.e. temporary or permanent in many demanding applications. But leakage current play vital role after data storage operation in semiconductor memories. Due to leakage current there may be chances of loss of information and it affects the system performance. Hence a leakage reduction technique proves to be an excellent alternative with memory circuit for minimized the leakage current.